Semiconductor devices are manufactured by forming active regions in a semiconductor wafer or workpiece, depositing various insulating, conductive, and semiconductive layers over the workpiece, and patterning them in sequential steps. The upper or last-formed layers of a semiconductor device typically comprise metallization layers that provide connections to underlying active regions and connections within and over the workpiece. The metallization layers typically comprise one or more layers of metal interconnect having conductive lines disposed within an insulating material.
One method of forming metallization layers is referred to in the art as a damascene process. Damascene processes are often used to form copper conductive lines because copper is difficult to subtractively etch, for example. In a damascene process for forming conductive lines, first, an insulating material or dielectric material is deposited over a semiconductor workpiece, and the insulating material is patterned using photolithography with trenches, holes, and/or channels. The trenches, holes, and/or channels are filled with a conductive material to form vias, contacts, plugs, and conductive lines within the insulating material. A chemical-mechanical polish (CMP) process or an etch process is typically then used to remove excess conductive material from over the top surface of the insulating material.
A damascene process may be single damascene or dual damascene. In a single damascene process, a single pattern is formed within a single layer of insulating material. The single layer may comprise a conductive line layer or a via/contact layer, for example. Multiple layers of interconnects may be formed by alternating conductive line layers and via/contact layers, each formed in a separate insulating material layer, for example.
In a dual damascene process, two patterns may be formed within a single layer of insulating material. For example, one pattern may be a conductive line layer and the other pattern may be a via/contact layer. A dual damascene process may comprise a via first or via last damascene process. A via last process is also referred to in the art as a ‘trench first’ process because trenches for conductive lines are formed first. In a via first dual damascene method, via patterns are formed within an entire thickness of the insulating material, followed by the formation of trenches for conductive lines within a top portion of the insulating material, over the via patterns. In a trench first dual damascene process, the trenches for conductive lines are first formed within a top portion of the insulating material, followed by the formation of the via pattern within the entire thickness of the insulating material beneath the patterns for the conductive lines.
The trend in the semiconductor industry is towards the miniaturization or scaling down in the size of semiconductor device features. Conductive lines in the metallization layers are being reduced as small as possible to increase device speed and accommodate the need for a reduction in size of semiconductor devices.
A problem in scaling down the size of semiconductor devices is that the photolithography techniques used to pattern the various material layers become challenging as device features shrink. Optical photolithography involves projecting or transmitting light through a pattern made of optically opaque areas and optically clear areas on a mask or reticle. As a light beam projects onto a wafer during patterning, interference of the light may be produced which can distort the shape of the desired pattern and deleteriously affect the critical dimension (CD) of the semiconductor device.
Optical proximity correction (OPC) is typically used to improve photolithography processes of semiconductor devices. One type of OPC involves using serifs on a photolithography mask to decrease diffraction effects. Another type of OPC is referred to in the art as scattering bars which are used for correcting and reducing the proximity effect in photolithography. The scattering bars comprise bar-like patterns that are formed on the photolithography mask. During exposure of a photoresist deposited on a semiconductor wafer, the scattering bars formed along the periphery of the pattern on the mask pass light and scatter the light to decrease the proximity effect on the design of the pattern desired.
Some semiconductor device designs have closely-spaced patterns on one part of a semiconductor die and widely-spaced patterns on another part of the same semiconductor die. For example, lines within a memory-array region of a chip are typically regularly and closely spaced, but in the peripheral sense-amplifier and logic circuitry, the lines are typically spaced farther apart and are more isolated. Proximity effects are particularly problematic in regions of a semiconductor device having isolated features in such a semiconductor device. In more densely populated regions of the semiconductor device, the photolithography exposure conditions are typically not as problematic.
If conductive lines in closely-spaced patterns have different dimensions than conductive lines in widely-spaced patterns due to proximity effects, the resistivity Rs of the conductive lines varies from widely-spaced patterns and closely-spaced patterns, which is undesirable because the electrical performance of the integrated circuit is deleteriously impacted.
Thus, what is needed in the art is a method of improving lithography techniques for integrated circuits having both widely-spaced and closely-spaced patterns.